This invention relates to programmable logic integrated circuit devices (“PLDs”), and more particularly to PLDs having transmitter circuitry for such purposes as outputting high-speed serial data signals.
PLDs are relatively general-purpose devices that various users may employ in any of a relatively wide range of different system applications. Each user of a particular PLD product “programs”, “configures”, or “customizes” that product to function in the desired way in that user's system. A PLD product may include one or more channels of transmitter circuitry (e.g., for use in outputting one or more high-speed serial data signals). A user may use such transmitter circuitry to output one or more signals for application to one or more other components of a system (e.g., via a printed circuit board or PCB on which the PLD and other components are mounted.)
Integrated circuits are becoming smaller, voltages used on such devices are becoming lower, and data rates are becoming higher. These trends are making it increasingly difficult to provide transmitter circuitry on PLDs that can function satisfactorily in a range of possible user applications. Some of the reasons for this are detailed in the next paragraph.
Transistor random mismatch tends to increase as integrated circuits are made smaller (so-called smaller “technology nodes”). Such mismatch can lead to random transmitter (“TX”) path offset. (Offset is a voltage under some or all conditions that is different than a desired reference voltage.) The impact of such an offset tends to become more important as data rates increase. This can be so for such reasons as reduced available timing margins and/or phase noise amplification over pre-existing PCB back-plane (“BP”) designs at high data rates. A signal that is initially distorted at the TX driver output (which is the BP input) may be further distorted after passing through the BP, which may have bandwidth that is significantly lower than the carrier frequency.
Another possible reason for TX output distortion may be output driver voltage. A PLD product may be designed for use in systems requiring an output driver to operate (for example) at either 1.2 or 1.5V. This may mean that the TX path is deterministically mismatched, which can lead to reduced TX driver matching and correspondingly reduced overall system performance.
TX drivers may have several output paths due to pre-emphasis requirements. Each such path needs to be considered as a potential source of mismatch. Depending on the user's link requirement, the number of taps and their strength at the output may differ, leading to possible variation in mismatch.